wpe1D.jpg (7174 bytes)
SSCD News Page

Home | Electrical Engineering Capabilites | Manufacturing Capabilities | Contact Us | News / Articles | Career Opportunities

Please click on the article of your choice.

Don't Build a House with a Shoe
Why Microvias?
Electronics Design Methodology Using VHDL
Meet the QA Director at SSCD

Don’t Build a House With a Shoe
By Jody Singleton, President SSCD

    Commonly, the approach for developing a printed circuit board is a sequential one, where a product is developed one step after another, with much trial and error: design, layout, build, test & debug, correct the design, correct the layout, build test & debug, correct the design, correct the layout, build test & debug and on and on it goes! This is very costly and time consuming and it doesn't necessarily result in the best result. Also, when you consider the fact that a product’s "shelf-life clock" is ticking from the minute you begin, it’s clear that problems become more costly and more time consuming the later in the process they are discovered. This reduces the chances of product viability. Plain and simple minimizing or eliminating errors and design or manufacturing iterations results in less costly product development. Iterations have the greatest impact in time-to-market delays.

    A McKinsey study found that a new product with a 5 year life cycle which is 6 months late to market can be expected to lose 33 percent of it’s total lifetime net profit. However, with a 50% development cost overrun, but on time to market, lifetime net profits are only reduced by an average of 4 percent!

    Today’s complex, higher performance electronic systems have the conflicting requirements of higher electrical performance yet with smaller weight and size. This has become the source of many development problems. Recently, a fortune 500 company did a study on the typical number of PCB spins that were required before it was released as a product. Here is what they found: only 5% of all boards required only one spin, 30% of all boards required 2 spins and 60% required 3 or more spins before being released as a product(!)

    So, what can be done to reduce the number of iterations of a board? Fortunately there is plenty. Consider using a combination of tools during design and layout to gain or keep your competitive advantage:

    As engineers face rise times in hundreds of picoseconds, dense routing, high speed clocks which create timing, EMI and signal integrity issues, analysis must now become an integral part of the design flow to ensure a high quality design. The outcome of doing this is very exciting because it reduces the number of board iterations needed. When one understands the exact issues that cause the need for board/design reiteration it becomes clear as to what can be done to reduce the number of iterations.

    As densities and data rates rise one can identify and avoid problems by using effective pre-layout analysis & constraints, post layout verification and concurrent analysis & simulation. The earlier the analysis is performed, the better, but even post layout analysis nets tangible results.

    The goal is to insure electrical functionality on the first pass of a board. If you really want to save time and money, invest at the pre-layout and post layout level. Studies show that it’s possible to cut an average of 2 weeks out of the development cycle, and the reduced number of iterations can save months. Performance and board quality are boosted. Re-spins are lessened or eliminated. What can be reasonably expected? For each design implementing these techniques, one re-spin is eliminated .

    Typically, there is initial resistance to using these technologies because they add time to the front end at layout. But, it soon becomes apparent that almost any level of analysis invested in at the front end pays off by saving more time at the back end, eliminating debug time and iterations. Frequently debug time can be cut in half.

    Finally, why would a team of experts be helpful even if you have your own in-house experts? Companies learn from their earlier problems, it is the new products with new technical issues that are their current road-blocks. Frequently these issues have been addressed in a different industry, but are not visible to the company not in that industry. Utilizing a team with experience and solutions from multiple markets gives the benefit of wider vision to your company.

    So "don’t build a house with a shoe" - use the right tools! In circuit design, this means use the appropriate tools that are available - they will save you time and money.

Top of Page

Simulation by R. D. Eicher, SSCD Principle Engineer

A common problem that all project managers and design engineers face today is "how to get new products to market faster, while maintaining quality and minimizing field returns"?

In the rush to get products to market, in-house and beta test cycle times are being reduced or in some cases eliminated. This often results in higher product returns, lower customer satisfaction, and ultimately lower profits.

Fortunately, there is a method to assure product performance and guarantee quality. Modern system simulation tools such as SPICE, HyperLynx, and VHDL offer a cost effective and fast alternative to the build of large quantities of beta hardware and the time consuming process of field testing.

At Single Source Circuit Design we offer a complete suite of high performance system simulation capabilities. Simulation packages such as:

As technology changes and the pace of product development increases, SSCD will maintain state-of-the-art simulation capabilities to support its customers and help assure market success.

Top of Page

Why Microvias?

by Jody Singleton, President SSCD

  Our core business is reducing product size and cost through the combined uses of electrical engineering technologies such as high-gate-count FPGAs and advanced packaging techniques such as microvias and buried components.

   Consider the high interconnect count of many of today's printed circuit boards due to "fly speck" SMT components, uBGAs, and other small scale packages such as Flip Chip and Chip on Board. These packages present challenges which demand reduction of traces, spaces and via size to complete the routing of all of the interconnects. Thru hole via technology becomes obsolete at a certain point due to the lack of availability of space to place the thru hole vias and the resultant issues and higher costs associated with drilling vias smaller than .010 with standard drilling techniques. A layout can quickly reach the point of "via starvation" where there is simply no more room to place vias.

   At less than 150 microns, microvias are a viable solution yielding lower manufacturing costs while allowing for higher interconnect density. According to ITRI an IPC* group that organizes research in the pcb industry, using microvias yields savings ranging from 8% to 70% in manufacturing costs. Ah, but the big question is: HOW do microvias lower the overall cost of manufacturing a pcb when taking into account lower yields than with conventional via technology? The reason? Fewer layers required and up to 75% overall area reduction resulting in a dramatically increased number of boards per panel.

  As an Officer for the Colorado Chapter of the IPC Designers Council, I encourage electrical and layout engineers to attend the Colorado Design Council. There is a wealth of knowledge presented on this and related topics quarterly.

   If you have any questions about our capabilities or IPC membership please call me at 303-288-8708 or e-mail me at Jody@sscd.com.

Top of Page


Electronics Design Methodology Using VHDL Hardware Description Language

By Ronald D. Eicher, SSCD Principal Engineer

  High-level synthesis of complex "highly integrated" digital circuitry has become as important to rapid product design, as "C" is to embedded processor development. The need to reduce hardware development cycles and to produce systems that are easier to maintain and change without the need for massive rework or PCB turns, is as important at this point, as the maintainability of firmware has been for years.

   Historically, electronics hardware design has involved the manual placement of gates and logic functions on schematics that could later be net listed for the production of PCB’s. This leads to an "almost" assembly language approach to design. This "almost" assembly language approach often results in obscure designs that can be difficult for others (such as test engineers, sustaining engineers, etc.) to understand. This lack of understanding on the part of support engineering personnel can often lead to errors during bug fixes or to the need for a complete re-design earlier than would have been necessary if a more understandable design methodology had been used initially.

   VHDL (VHSIC Hardware Description Language) was developed during the 1980’s to assist in the top down design of high-speed digital electronics. Since that time it has been adopted as IEEE-1076 and is now supported by virtually every CAD tool manufacturer in the world. VHDL gives the digital electronics designer a procedural design methodology that is similar to that used by "C" or Pascal designers, and provides a powerful simulation system that leads to higher quality designs and less rework. Furthermore, the ability to design complex digital circuitry in a high level language has lead to the explosion of programmable logic devices such as FPGAs, CPLDs, and PLAs. With modern programmable devices, entire systems can now be designed on a chip without the need for combinatorial logic and can be changed at will without rework or artwork turns. The ability to change logical functionality in the field allows the implementation of design fixes, feature enhancements and revision changes without the need for hardware changes or even for the device to be returned to the factory.

  At Single Source Circuit Design, we produce turnkey systems for customers as diverse as aerospace and consumer electronics. The common denominator between such diverse system and customers is the use of programmable components such as embedded microprocessors and field programmable devices. One of the key components of our success is the use of high level programming languages such as "C" and VHDL. This design methodology is vital to our customers to insure that product life cycles are maximized and that system test and manufacturability is assured.

Top of Page

Meet the QA Director at SSCD

Chuck Allen, QA Director SSCD

   SSCD has a Quality Director: me-Chuck Allen by name. I'd like to tell you something about myself and why SSCD has undertaken the commitment of having a QA Director.

   First, something about myself. I've been in the profession for over thirty years. I have been certified as a Quality Engineer by the American Society for Quality Control (now ASQ) and I have recently done consultation for NASA. In my spare time I'm building a straw bale house which I love to talk about; I also enjoy model railroading and sailing.

   Now onto the real question "Why is a quality system so important to SSCD?" For one thing, SSCD has been developing QA procedures for its engineering area for seven years, however, as SSCD has grown from a small design shop to a full fledged engineering firm, the demands on its QA have required the retention of someone like me. This is necessary not only to keep apace with the demands of our projects but it’s also in keeping with the founder’s goals, to take QA to a whole new level for an engineering services firm.

The problem is simple. The customer wants his product to be of the best value: best quality, best cost and in the shortest practical time. My job is to address this problem from the standpoint of QA-to evaluate our procedures and policies so as to arrive with a QA system that is an optimum balance between these two functions in creating the most efficient quality-producing system.

    So what is "quality"? It's more than just doing a good job: it's doing the same thing in the same measurable way to achieve results as consistently as possible. This means developing and implementing checklists and procedures to follow which define a "good job". This also requires uninvolved third party audits to verify that the checklists and procedures are giving the results expected. And finally, customer feedback determines the level of "good" that the job is achieving.

    SSCD is developing an ISO 9001 compliant system. Having a quality system that follows a recognized national standard allows both customers and vendors to know what to expect of us. It defines how we do business.

   By establishing what documentation is considered necessary for retention and archival storage, a quality system can reduce costs for redesign and reuse. Standardized documentation requirements will also allow the data legacy of a project and/or customer to remain with the organization. It also allows a job to be understood by each individual involved in it, thus insuring consistency of the practices and results. The final goal of the system then is to help SSCD better serve its customers.

   If you have any comments or suggestions I would appreciate your feedback. Please send them to SingleSource@sscd.com with "QA" in the subject line.

Top of Page

Home | Electrical Engineering Capabilites | Manufacturing Capabilities | Contact Us | News / Articles | Career Opportunities

Send mail to Webmaster with questions or comments about this web site.